A processor of a computing system may access a data element by issuing a transaction, such as a memory read transaction or a memory write transaction, on a bus of the computing system. The transaction may include an identifier of the type of transaction and an address identifying the data element accessed by the transaction. The address of a transaction issued on the bus may have a width in address bits that is dependent on the implementation of the bus. The width, N, of the address may define an address space that has 2N data elements.
The address space may be divided into various ranges. For example, the computing system may include several local devices and a respective range may be allocated to each local device. In addition, the computing system may include several peripheral devices and another respective range of the address space may be allocated to each peripheral device. An address decoder may receive the address of a transaction from the processor and the address decoder may determine whether a local range includes the address. Expeditious handling of a transaction by the computing system may require that the address decoder quickly determine whether a local range includes the address.
Quick address decoding may be provided for a computing system by using one address bit to split the address space between the local devices and the peripheral devices. For example, a value of zero for the most significant bit of an address may indicate that access to the corresponding data element for the address is provided by a local device and a value of one for the most significant bit of an address may indicate that access to the corresponding data element is provided by a peripheral device. Thus, the address space is split into a lower half allocated to local devices and an upper half allocated to peripheral devices.
Many applications for a computing system require complex allocations of the address space to various local and peripheral devices. Flexible allocation of an address space, including complex allocations of the address space, may be desirable in many other applications. An example complex allocation of the address space interleaves a local range between two peripheral ranges. A computing system with a complex allocation of the address space may require quick address decoding. However, distinguishing between local and peripheral ranges using a single bit may not be feasible for these complex allocations of the address space.
The present invention may address one or more of the above issues.